With rapid development of semiconductor technology and substantial improvement of microelectronic chip integration level, the design and process for integrated circuit has entered a nano-scale era. The gate oxide, as a core of a MOS device, plays a pivotal role in the assessment of quality and reliability of the MOS devices. The generation of interface traps of the gate oxide layer decreases mobility of the device and degrades performance of the device. Therefore, it's necessary to monitor the interface traps of the gate oxide layer during the process flows. Commonly used testing structure for interface trap density of gate oxide measurement is an oxide capacitance structure or a MOSFET device, which is shown in FIG. 1a as a 2-terminal capacitor element structure including a gate and a substrate, and is shown in FIG. 1b as a 4-terminal MOSFET device structure including a source, a gate, a drain and a substrate, where Tox is the gate oxide thickness of the device. Conventional testing methods usually conduct measurements to gate oxide layer testing structures of n-type MOS device and p-type MOS device respectively, and a testing structure similar to that in FIG. 1a and FIG. 1b usually is a single gate oxide capacitor or a MOSFET device, therefore only measuring the densities of gate oxide interface trap on different testing structures can obtain both information on densities of interface traps for n-type MOS device and p-type MOS device involved in the CMOS integrated circuit technology. In addition, one existing CMOS process can provide multiple gate oxides with different thickness for design flexibility, which usually requires a considerable number of sample tests to obtain comprehensive information on quantity of gate oxide layer. This results in time-consuming measurement and low efficiency. Moreover, conventional testing methods require the use of instruments such as pulse generator, and hence result in high cost of test equipment.